Time Sensitive Networking - A TSN Implementation on Intel FPGA Base

Whitepaper 02: Time Sensitive Networking - A TSN Implementation on Intel FPGA Base#

Fraunhofer IPMS - Wireless Microsystems

Author: Marcus Pietzsch

Currently being developed by the IEEE, Time Sensitive Networking (TSN) is a set of standards aimed at increasing the degree of determinism in switched Ethernet networks according to existing IEEE 802.1 and 802.3 standards. In essence, TSN looks to realize Ethernet networks with:

  • guaranteed end-to-end latencies for real-time critical data traffic
  • transmission of (time-) critical and uncritical data traffic over a converged network
  • low packet losses
  • low latency fluctuation (jitter)

Content

  • Introduction
  • TSN In Use – An Example
  • TSN Implementation – Intel FPGA Basis
  • Hardware Description
  • Software Description
  • Summary
  • About Fraunhofer IPMS

 

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Time Sensitive Networking - A TSN Implementation on Intel FPGA Base

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