Back-End-of-Line Integration (BEoL)

Fraunhofer IPMS operates a state-of-the-art 300 mm Back-End-of-Line (BEoL) integration platform in Dresden, Germany, enabling the development, integration, and scaling of next-generation semiconductor interconnect technologies in a production-relevant cleanroom environment.

Our 300 mm pilot-line infrastructure bridges the gap between fundamental research and industrial semiconductor manufacturing. It allows industry partners, research institutions, and funding agencies to bring innovations from early-stage concepts into scalable process modules under Fab-like conditions.

We provide access to a complete CMOS-compatible BEoL process chain, including advanced copper damascene integration, barrier and seed layer deposition, electrochemical plating, and chemical-mechanical planarization (CMP). This enables the realization and optimization of high-performance interconnect architectures for advanced technology nodes.

Beyond established process flows, Fraunhofer IPMS actively develops and integrates novel materials, low-k and ultra-low-k dielectrics, and heterogeneous integration approaches. These activities support the transition toward more complex system-in-package and beyond-CMOS concepts.

A key feature of the platform is the flexible “flying wafer” approach, enabling seamless exchange between external fabs and Fraunhofer IPMS processing. This ensures high process relevance while maintaining maximum experimental flexibility for research-driven innovation.

The BEoL integration environment is complemented by extensive metrology and characterization capabilities, enabling full process control from thin-film properties to device-level electrical performance.

With its unique combination of industrial 300 mm infrastructure, advanced process expertise, and research-driven innovation, Fraunhofer IPMS provides a powerful platform for accelerating semiconductor technology development across the entire value chain.

Complete 300 mm BEoL Process Line

• Full access to production-like equipment to test innovations against matched Fab PORs
• Established flying wafer protocol (Fab – IPMS – Fab) allows partial or full flow coverage
• Streamlined processing with low Q-time for high sensitivity investigations
• Evaluation of sub 20nm structures and components

Our Expertise

Processes integration

• Alternative interconnect materials / substrates / concepts
• 14 nm BEol modules

Device integration

• NVM integration, e.g., FeFET, MRAM / Racetrack, RRAM
• Passive devices, e.g. Capacitor, Varactor