Chemical Mechanical Planarization (CMP)

Fraunhofer IPMS offers comprehensive Chemical-Mechanical Planarization (CMP) capabilities for both 200 mm and 300 mm wafers in its state-of-the-art CMOS cleanrooms. Our CMP lines support advanced logic, memory and specialty applications and are available for joint development projects, process qualification and customer-specific process optimization.

Highly integrated circuits consist of many material layers. During fabrication, the wafer surface must be repeatedly planarized to ensure sufficient process windows for critical steps such as lithography and etching. Planarization is also essential to achieve defined feature dimensions and, ultimately, reliable device performance. CMP is the industry-standard method to achieve this level of planarity.

With continuous scaling of semiconductor technology and the introduction of new materials, the demands on CMP accuracy and process control are steadily increasing. Fraunhofer IPMS combines industrially relevant equipment, dedicated test structures and extensive metrology to develop, qualify and optimize CMP processes for current and future technology nodes.

In the 300 mm cleanroom, Fraunhofer IPMS provides industry-relevant CMP processes and patterned short-loop wafers for development and qualification.

Applications

• Cu/Barrier CMP (Damascene process)
• ILD planarization (interlayer dielectrics)
• STI polish (Shallow Trench Isolation)

Capabilities & Advantages

• Wide process space via combination of chemistry and mechanics
  • High material selectivity
  • High topography selectivity
• Systematic process-window and design dependence studies using dedicated test chips
• Process variation via pads, slurries and process parameters
• Evaluation of new equipment and materials under industry-standard conditions
• Pre- and post-processing for step optimization
• Inline metrology and professional contamination management
• Professional IP management and close industrial collaboration
• Availability of patterned 300 mm short-loop test wafers 

The 200 mm CMOS cleanroom combines multiple CMP platforms with a high-clean grinder for flexible process and material studies.

AMAT Mirra 3400 with Desica Cleaner

• 5‑zone contour head for profile tuning
• Megasonic Hot SC1, NH₄OH brush clean, IPA dryer
• Optical endpoint detection (laser)
• Default processes: stop and blind CMP for SiO₂, Poly-Si, Si, resist

Ebara F‑REX200M2

• 4‑zone Ai head, buff table for post-CMP touch-up
• Single-wafer megasonic cleaning, variable chemical clean (with/without brushes)
• Endpoint detection: spectral lamp, motor current, RECM
• Default processes: stop and blind CMP for SiO₂, Poly-Si, W

Disco High Clean Grinder DGP 8761 (Grinding + CMP)

• Dual-spindle Si grinding (coarse/fine) with integrated 2‑platen CMP
• Cleaning of backside, edge and surface (brushes + NH₄OH, H₂O₂, DI water)
• Endpoint: contact gauge (thick Si) and optical gauge with in-situ profile optimization (< 75 µm)
• Default processes:
  • Si bulk down to 250 µm (TTV ~2.5 µm)
  • Si top layer down to 5 µm

Fraunhofer IPMS supports industry and research partners along the full CMP development chain:

• Process development & optimization
  • New CMP processes for materials, layer stacks and designs
  • Adaptation of existing recipes to new designs or consumables
• Screening & evaluation
  • Systematic comparison of slurries, pads, chemistries and parameters
  • Assessment of CMP and cleaning equipment under realistic conditions
• Pre-/post-processing & integration
  • Surface preparation and post-CMP cleaning for defect and uniformity control
  • Integration of CMP and thinning/grinding into complete process flows
• Metrology & characterization
  • Inline and offline measurements (thickness, TTV, topography, defects)
  • Use of test chips and short-loop structures for process-window and design analysis