Chemical Mechanical Planarization (CMP)

The CMP Process

Highly integrated circuits, like logic and memory chips, consist of many material layers. In the course of manufacturing the surfaces have to be planarized over and over again to obtain sufficient process windows for critical processes like lithography and etching. Furthermore planarization ensures defined sizes of the structures, thus in the end reliable functioning of the electronic elements. Chemical-mechanical planarization (CMP) is the state of the art to reach the necessary planarity. The continuous shrinking in the semiconductor technology goes along with a higher demand for accuracy, as well as a higher number of materials used. Therefore it is necessary to understand the various CMP processes and to develop novel processes for newly introduced materials to be able to fulfill the demands of the coming technology nodes.

Applications

• Combination of chemistry and mechanics offers large process diversity (high material selectivity, high topography selectivity)
• Standard CMP processes at Fraunhofer IPMS Cu/Barrier CMP (Damascene process);
• ILD planarization; STI polish
• Process variation depends on consumable type and state (e.g. polish pad, slurry)
• CMP processes are highly design-dependent, requiring dedicated test chips for systematic process window characterization

Advantages

• Evaluation of new equipment and materials under industry standard conditions
• Pre- and post-processing for optimization of individual process steps
• Inline metrology
• Professional contamination management
• Professional IP management and licensing
• Close connection to industry
• Availability of patterned 300 mm short loop test wafers