TSN/A Conference 2021

Fraunhofer IPMS presents a scalable TSN multiport switch at the TSN/A conference

Press release /

The TSN/A conference has become one of the most important international meetings of experts in the field of industrial Ethernet standards. With the help of Time Sensitive Networking (TSN), standard Ethernet gains a new dimension through time-synchronous and deterministic data transmission. How these technologies will affect industry, automotive and the audio-video-consumer world are the central questions of this year's conference on September 29 and 30. Marcus Pietzsch from the Fraunhofer Institute for Photonic Microsystems IPMS will take a closer look at the latency of time-critical networks in his workshop.

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Fraunhofer IPMS develops IP Cores for the control and prioritization of data.

By using TSN, 5G and the standardized, secured communication protocol OPC UA, a new transmission medium is emerging from standard Ethernet, which is being widely used especially in application areas such as industrial production, automotive and pro AV/consumer IP networking. This year's TSN/A conference will highlight both the technological aspects and application-specific topics that are relevant in different markets and industries. The program will focus on time-sensitive networks and applications for Cyber Physical Systems, Industrial Internet of Things, Real-Time Audio & Video and Intelligent Transportation Systems.

Fraunhofer IPMS develops platform-independent TSN IP cores for FPGA and ASIC implementations and offers development services for customer-specific system developments based on them. The latest development is a multiport TSN switch IP core. In its standard configuration, the core provides four external ports and one internal CPU port. However, the flexible design of the core allows scaling up to 16 ports.

At TSN/A, Marcus Pietzsch, group leader for IP cores and ASICs at Fraunhofer IPMS in Dresden, will use IPMS' TSN IP cores in a workshop to discuss latency within time‑critical networks. "In principle, TSN can be used in any system where predictable, deterministic, time behaviour is required," Pietzsch explains. "The focus here is particularly on industrial applications, control systems, data logging, embedded systems, security systems, audio and video processing, and telecommunications applications. However, these diverse application scenarios have very heterogeneous latency requirements and therefore require flexible solutions." This workshop will provide a brief overview of Ethernet TSN and its standards. The typical sources of latency in a TSN network will be explained and practical tips for reducing unwanted time delays will be given. Pietzsch also explains how designers can use IP cores for the development of industrial or automotive networks, which is finally visualized in a live demo of an example setup.

The now sixth TSN/A conference, which will be held in virtual format for the second time, will be jointly organized by the Avnu Alliance in cooperation with the German trade journals Computer&AUTOMATION and Elektronik automotive on September 29 and 30, 2021.


About Fraunhofer IPMS

The Fraunhofer Institute for Photonic Microsystems IPMS stands for applied research and development in the fields of industrial manufacturing, medical technology and improved quality of life. Our research focuses on miniaturized sensors and actuators, integrated circuits, wireless and wired data communication, and customized MEMS systems.

Fraunhofer IPMS has years of experience in designing and engineering IP cores for automotive communication and has a family of TSN IP cores. Many users worldwide use Fraunhofer IPMS IP cores in the automotive, aerospace, and automation industries, among others. The multidisciplinary IP design team of Fraunhofer IPMS with expertise in computer architectures, network structures, RTL design and implementation of electronic systems is also available as a competent development partner for application-specific adaptations of the IP cores as well as their integration into complex network architectures.­