QUASAR - semiconductor quantum processor with shuttling-based scalable architecture

QUASAR - semiconductor quantum processor with shuttling-based scalable architecture

Project duration: 2021 - 2025

In this project, an architecture for quantum computers without geometric scaling limits will be realized using semiconductor technology that is industrially available in Germany. Up to now, scaling of qubits has been difficult because fabrication processes suffer from low yield, throughput and reproducibility due to, for example, the lift-off processing of quantum gates or the characterization of only sporadically produced samples. This is where the project comes in.

Fraunhofer IPMS participates by using adapted processes from CMOS fabrication. Based on many years of experience in electron beam lithography and in close cooperation with Infineon, deal with the fabrication of the complex "Gate 1" quantum gates. Optimized device structures with the highest possible homogeneity at the substrate level are to be made available via several interration steps and under consideration of fabrication-technical possibilities. This would not be achievable with proven laboratory methods such as lift-off processes in the required quality and quantity, related to structure scalability.

Finally, the project will demonstrate the functionality of the individual quantum devices: One-qubit gates with 99% fidelity, two-qubit gates with 95% fidelity, spin-coherent "shuttling" of electrons, and optional coupling of up to five qubits.

In collaboration with: