APECS-Pilotlinie

Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems

The APECS pilot line at a glance:

As part of the EU Chips Act the APECS pilot line marks a major leap forward in strengthening Europe’s semiconductor manufacturing capabilities and chiplet innovation. By providing large industry players, SMEs, and start-ups with easier access to cutting-edge technology, the APECS pilot line will build a strong foundation for resilient and robust European semiconductor supply chains.

Within APECS, the institutes collaborating within the Research Fab Microelectronics Germany (FMD) are working closely with other European partners, making a significant contribution to the European Union´s goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in the semiconductor technologies.

Fraunhofer IPMS plays a crucial role in the APECS pilot line and will drive the project's goals in chiplet development and integration technology. One part deals with the design of the chiplet system, where we build innovative system architectures for computing, artificial intelligence and MEMS sensors/actuators. The second major part covers new chiplet integration technologies on 200 and 300 mm wafers, including 3D stacking and 2.5D wafer-level integration, ultra-high density functional interposers and CMOS and MEMS/non-silicon chiplets. A major part of our contribution is the development of quasi-monolithic integration (QMI), which will set new standards in chiplet integration technology.

Within the framework of APECS, we are also working on the implementation of functional safety requirements in the design of integrated circuits. To this end, we are developing design flows for the modeling of IP cores, which we are implementing using our RISC-V and TSN IP cores as examples.

Research in the areas of characterization, testing and reliability round off our research portfolio.