Fraunhofer Institute for Photonic Microsystems
Fraunhofer Institute for Photonic Microsystems

Deposition

Semiconductor Process Services

Deposition

Semiconductor Process Services

Atomic Layer Deposition (ALD)

Atomic Layer Deposition (ALD) is a thin film deposition method which is based on temporally or spatially separated surface reactions resulting in cyclic self-limiting monolayer coverage. Due to its unique characteristics like precise film thickness control, excellent uniformity and conformity as well as lower deposition temperatures compared to other CVD methods, ALD has become more and more state-of-the-art for an increasing number of applications.

© Fraunhofer IPMS
STEM analysis of a highly conformal high-k oxide laminate coating by ALD for MIM capacitor applications in high aspect ratio structures (>50:1).
We are offering our leading edge high-k technologies for 300 mm (12 in) and smaller wafer sizes in an unique competence center for Atomic Layer Deposition - bridging the need for initial high investment for entering the field of ALD for small to large sized companies. We are addressing the needs of fast and accurate electrical results for process development or failure analysis, customized tests and characterization services on wafer level as well as the scale up of novel precursor chemistries. From early lab results to 300 mm (12 in) processing equipment that is qualified to run device wafers and support pilot ramp into manufacturing, the Screening Fab is covering all process steps.
 
  • ALD deposited High-k oxides and electrodes for: stand-alone memory and embedded memory (SRAM, DRAM, RRAM and FRAM)
  • HfO2, TiN and TaN for High-k / Metal Gate (HKMG) for different flavors: high-k first, high-k last, FDSOI and FinFET transistor technologies
  • Fully CMOS-compatible ALD deposited HfO2 based ferroelectrics for FeFET NVM memory
  • Passive components integrating ALD deposited 3D high-k MIM capacitors (for buffering and decoupling purposes in chip (System on Chip - SoC) or package (System in Package - SiP) level)
  • PEALD oxide and nitrides for the transistor module and for sub 28 nm double patterning schemes such as SADP
  • Hardmask for high aspect etching in silicon and oxide
  • Passivation layers for photovoltaics 
  • ALD processes for MEMS/MOEMS applications: etch stops, wear resistant layers, optical layers (Bragg mirror) and sensor materials (ISFET)

Rapid ALD precursor screening

  • Fast screening by employing in-situ analytics (QCM and QMS)
  • Fundamental research on nucleation fi lm growth and step coverage
  • Scale up to from small samples up to 300 mm wafers
  • Single wafer and Large Batch ALD
  • Crossflow, Showerhead and Batch Furnace process chambers
 

Materials research and development for:

  • High-k oxides (HfO2, ZrO2, TiO2, Al2O3 ,SiO2)
  • Metals and metal nitrides
  • Cu BEoL barrier/seed
  • Hardmasks for high aspect ratio etching in silicon and oxide
  • Liners and spacer
  • Low cycle-time test chip for electrical read out for MIS / MIM devices 
  • Planar and 3D high-aspect ratio structures

Thermal ALD

Applications:

  • Dielectrics/ passivations: SiO2, Al2O3
  • High-k materials: HfO2, ZrO2
  • Ferroelectric materials: HfO2 doped with Al, Zr, Si, La

Substrate:

  • 300 mm silicon wafers,
  • Single wafer process

Tools:

  • ASM Pulsar, Jusung Eureka 3000

Plasma-Enhanced ALD (PE-ALD)

Applications:

  • Dielectrics/passivations: SiO2, Al2O3, TiO2
  • High-k materials: HfO2
  • Li-based materials: LiPON, LTO

Substrate:

  • 300 mm silicon wafers
  • Single wafer process

Tools:

  • ASM EmerALD, Oxford FlexAl

Batch ALD

Applications:

  • Electrode material: TiN

Substrate:

  • 300 mm silicon wafers, Batch process (up to 35 wafers per run)

Tools:

  • ASM A412

Chemical Vapor Deposition

Chemical Vapor Deposition (CVD) is a thin-film deposition technique used to form solid films from gaseous reactants. Precursor gases are introduced into a reactor, where they adsorb onto the substrate surface and chemically react into a solid film. Gas-phase reactions are activated either by thermal energy (thermal CVD) or by plasma ionization (plasma-enhanced CVD). Depending on the process conditions, CVD can produce amorphous, polycrystalline up to high-quality epitaxial films. The technique ensures high throughput, with rapid deposition rates and excellent uniformity across large-area substrates.

© Fraunhofer IPMS
Film growth during CVD process.

What we offer:

  • Custom processing for broad range of CVD applications
  • High-throughput deposition with precise control over films properties
  • Innovation support for deposition on 300 mm R&D
  • Scalable for mass production / fab-ready technology

In case of plasma-enhanced CVD:

  • Low-temperature processing for BEOL and temperature-sensitive substrates
  • Plasma-engineered film properties (tunable density, stress, composition)

Plasma-Enhanced CVD (PE-CVD)

© Fraunhofer IPMS
ASM XP8 Dragon at Fraunhofer IPMS.

Materials:

  • Dielectrics: SiO2, SiN, SiON
  • Low-k materials: SiCOH (BD-1), ULK (BD-2) 
  • Passivation and Barrier low-k materials: SiC, SiCN, a-Si, a-C

Applications:

  • Interlayer dielectrics for CMOS devices
  • Diffusion and moisture barriers in IC fabrication
  • Hard mask and etch stop layers for lithography
  • Stress engineering layers
  • Interconnect dielectrics for advanced BEOL integration
  • RC delay and power consumption reduction in high-speed logic
  • Porous ultra-low-k dielectrics for technology scaling in modern ICs
  • Active and structural material for TFTs, MEMS and sensors

Thermal CVD

© Fraunhofer IPMS
ASM A412 at Fraunhofer IPMS.

Materials:

  • TiN (pulsed CVD / ALD-like)
  • Bor/phosphor doped Si
  • Polycrystalline Si and Ge
  • Bor/phosphor doped SiGe

Applications:

  • Conformal metal gate electrodes – excellent step coverage
  • In-situ doped low-resistance films
  • Strain-engineered transistor channels and gates
  • Bandgap-tunable semiconductor electrodes
  • Advanced logic node integration

Metal-Organic Chemical Vapor Deposition (MO-CVD)

© Fraunhofer IPMS
300 mm CMOS cleanroom at Fraunhofer IPMS.

Materials:

  • Metals: Co

Applications:

  • Seed / liner layers for Cu or Co interconnects - excellent step coverage
  • Direct Co interconnects

Epitaxial Growth

Epitaxy is a flexible crystal growth technique in which the crystal structure and orientation of the substrate are continued during layer formation, resulting in high-quality single-crystalline films. In leading-edge semiconductor manufacturing, epitaxy is essential for bandgap engineering through defect-free heteroepitaxial stacks of different materials, as well as for strain engineering, where lattice mismatch between substrate and grown layer is used to enhance carrier mobility in transistor channels. In addition, in-situ doped epitaxial source and drain layers enable the formation of highly abrupt p–n junctions, which are critical for advanced device performance.

© Fraunhofer IPMS
(Top) TEM image of a p-channel MOSFET with embedded SiGe source and drain. (Bottom) High-resolution TEM image of the interface between the epitaxial silicon–germanium layer and a silicon (100) substrate.

Fraunhofer IPMS is equipped with a unique 300 mm batch reactor for selective epitaxy. Silicon and silicon-germanium layers can be provided from nanometer to micrometer thickness scales. Selective epitaxy and in situ doping technologies enable innovative device integration schemes. Additionally, batch processing yields significantly reduced cost of ownership as well as low thermal budget without compromising wafer throughput. In combination with state-of-the-art equipment for wafer patterning, cleaning and characterization, Fraunhofer IPMS offers a flexible platform for the development of single processes, process modules and integrated devices.

 

What we offer:

  • Atomically ordered layer growth
  • Strain and band gap tunable by composition adjustment
  • Batch processing for reduced cost of ownership
  • Selective epitaxy for development of innovative devices
  • Flexible platform for joint technology development
  • Full lab support for epitaxial layer characterization

Applications:

  • Embedded SiGe for strain generation in transistor channels
  • In situ doped low resistivity source/drain contacts
  • Single crystalline, band engineered heterostructures and super lattices
  • Formation of active regions in e.g. SiGe HBT or BiCMOS devices

Physical Vapor Deposition (PVD)

Physical Vapor Deposition (PVD) is a technique used to deposit thin films by the physical transfer of material from a condensed phase to a vapor phase and then back to a condensed phase onto a substrate. This process typically involves the use of high vacuum conditions to facilitate the evaporation or sputtering of the source material, which then condenses as a thin film on the substrate.

© Fraunhofer IPMS
Physical Vapor Deposition (PVD) process.

SpuC02-02 (FEOL + MRAM materials)

Available materials and alloys:

  • FEOL: Si, Co, Hf (N, Ox), Zr (N, Ox), Ti (N, Ox), cosputtering of 2 materials is possible, deposition on hot wafer (up to 400°C)
  • MRAM: CoFeB, CoFe, W, Mo, MgO, Ta, Co, Pt, Ru, Ni
  • Other processes available in the tool: degas in Ar atmosphere (RT - 440°C), surface preclean (etching) with Ar plasma, annealing in vacuum (up to 450°C)

Metrology:

  • OBM

Spuc02-01

Available materials:

  • Ta(N), Cu, Ti
  • Other processes available in the tool: Mo-CVD Co, ALD, TaN, degas/Annealing in Ar/H2c atmosphere (up to 440°C)

Metrology:

  • XPS

200 mm Deposition

© Fraunhofer IPMS
  • Atomic Layer Deposition ALD
  • LP-CVD 
  • PE-CVD
  • PVD sputtering
  • Evaporation
  • Oxidation
  • Rapid Thermal Annealing
  • Vapor phase deposition

Our Equipment:

 

Fraunhofer IPMS

200 mm MEMS Cleanroom Infrastructure

more info
 

Fraunhofer IPMS

300 mm CMOS Cleanroom Infrastructure

more info

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