Ethernet IP Cores

IP Core for TSN Mulitport Switches – TSN-SW

Engineered for deterministic industrial Ethernet, this TSN multiport switch delivers precise timing and predictable performance for factory automation, robotics, and energy systems. It combines ultra‑low‑latency cut‑through forwarding with standards‑based TSN, scalable port counts, and robust software support for fast, reliable integration.

Features

• Scalable port density: up to 24 external ports + 1 host port (variants from 2 external + 1 internal)
• Ultra‑low‑latency cut‑through switching for time‑critical traffic
• Up to 8 traffic classes with IEEE 802.1Qav credit‑based shaping and 802.1Qbv time‑aware scheduling
• IEEE 802.1AS‑2020 time sync, grandmaster‑capable with nanosecond‑level accuracy
• 802.1Q VLAN tagging with configurable VLAN‑PCP to TSN‑queue mapping (QoS by PCP)
• Integrated triple‑speed low‑latency Ethernet MAC; 10/100/1000 Mb/s
• Flexible interfaces: Host (AXI, Avalon ST/MM, APB) and PHY (MII, GMII, RGMII)
• Software package: FreeRTOS driver/HAL, PTP/AS‑2020, CLI, and example projects

Data Sheet: TSN-SW for Multiport Switches

IP Core for TSN Switched Endpoint – TSN-SE

Designed for deterministic industrial Ethernet devices, this TSN switched endport delivers precise timing and predictable performance for motion control, robotics, and machine networking, combining ultra‑low‑latency forwarding with standards‑based TSN and streamlined software integration.

Features

• Ultra‑low‑latency cut‑through switching for time‑critical traffic
• Up to 8 traffic classes with IEEE 802.1Qav credit‑based shaping and 802.1Qbv time‑aware scheduling
• IEEE 802.1AS‑2020 time sync, grandmaster‑capable with nanosecond‑level accuracy
• 2 external + 1 internal port for flexible endpoint/topology integration
• 802.1Q VLAN tagging with configurable VLAN‑PCP to TSN‑queue mapping (QoS by PCP)
• Integrated triple‑speed low‑latency Ethernet MAC; 10/100/1000 Mb/s
• Flexible interfaces: Host (AXI, Avalon ST/MM, APB) and PHY (MII, GMII, RGMII)
• Software package: FreeRTOS Driver/HAL, PTP/AS‑2020, CLI, and example projects

Data Sheet: TSN-SE for Switched Endpoint Devices

IP Core for TSN Endpoint – TSN-EP

Built for deterministic industrial Ethernet endpoints, this TSN-enabled device delivers precise timing and predictable performance for motion control, robotics, and smart sensors, with ultra-low latency and standards-based TSN for easy integration.

Features

• Ultra-low-latency cut-through switching for time-critical cycles
• Up to 8 traffic classes with IEEE 802.1Qav credit-based shaping and 802.1Qbv time-aware scheduling
• IEEE 802.1AS-2020 time sync, grandmaster-capable with nanosecond-level accuracy
• 1 external + 1 internal port for compact endpoint/topology integration
• Integrated triple-speed low-latency Ethernet MAC; 10/100/1000 Mb/s
• Flexible interfaces: Host (AXI, Avalon ST/MM, APB) and PHY (MII, GMII, RGMII)
• Software package: FreeRTOS Driver/HAL, PTP/AS-2020, CLI, and example projects

Data Sheet: TSN-EP for Endpoint Devices

TSN Netleap Evaluation Kit 

• Altera based FPGA-Board
• SD-Card with image
• Power supply 5V/2A
• Two-part housing
• USB-PPS-Cable
• User Guide

This kit comprises both harware and IP Core.

TSN Xilinx ZCU102 Evaluation Kit

• AMD Xilinx FPGA-Board ZCU102
• SD-Card with image
• Power supply
• 2 micro USB cable
• USB hub
• Ethernet cable
• SFP adapter (SW: 4, SE: 2, EP: 1)
• User Guide

This kit comprises both harware and IP Core.

TSN Evaluation Bit File (for Xilinx ZCU102 or Netleap Board)

• FreeRTOS Driver/HAL
• FreeRTOS PTP/AS-2020
• FreeRTOS Command Line Interface
• 802.1Q VLAN Switch functionality (SE, SW)
• Optional Free RTOS Qci
• Optional FreeRTOS Qcc
• Optional FreeRTOS IwIP integration
• Optional TSN Linux Embedded Driver Reference Design

This kit consists only of the IP Core (no hardware).

The IP design implements an Ethernet Media Access Controller (MAC) that is compatible with IEEE 802.3 and IEEE 802.3-2002 specifications at 10/100 Mbps and 1 Gbps. With its extremely low input and output latency, the Low Latency Ethernet MAC Core is ideal for implementation in TSN Ethernet nodes and other devices that require low latency when receiving and sending Ethernet frames. The core is certified as ASIL-D-ready according to ISO 26262 for functional safety in automotive applications.

Features

• IEEE 802.3 compliant, triple‑speed Ethernet MAC (10/100/1000 Mbps)
• TSN-ready: enables high‑precision time synchronization
• Deterministic low latency: 10-cycle TX, 6-cycle RX
• Jumbo frame support for higher throughput
• Full/half‑duplex point‑to‑point operation
• 10BASE‑T1S support (single‑pair Ethernet)
• Broad PHY connectivity: MII (10/100), GMII (1G), RGMII (10/100/1000)
• MDIO interface for PHY configuration and management

The MACsec IP Core supports highest data rates and implements IEEE 802.1AE-2018 Layer 2 security standard for authentication, confidentiality, and integrity between LAN hosts. MACsec permits authorized nodes to communicate, encrypts transmitted data for confidentiality, and provides cryptographic mechanisms to ensure data integrity. It is compatible with the Fraunhofer IPMS LLEMAC IP core, any other Ethernet MAC IP core, or can operate as a standalone solution.

The MACsec IP core can be provided platform-independently for all FPGA platforms and any foundry technology. Fraunhofer IPMS also offers services to extend IP cores as well as to develop complete customer specific subsystems. 

Fraunhofer IPMS has more than 20 years of experience in the development and licensing of IP cores and several hundreds of users worldwide. Most customers are from the automotive, aerospace and manufacturing industries.

Features

• Compliance with IEEE Std 802.1AE-2018
• Supports authentication and authenticated encryption
• Speeds from 10M to 50G, >50G via parallel pipelines on-request
• Supports NIST encryption standards (US)
• Key width: 128 & 256 bits (supports AES-GCM and AES-GCM-XPN)
• VLAN-in-Clear
• Full duplex or Half duplex architecture
• Secure Channel support up to 216
• Detailed statistics and error reporting
• AXI stream interface for MAC data
• Different host controller interfaces for configuration (APB, AHB, …)
• Additional user specific sideband information
• Configurable Header Prefix
• Fully synchronous and synthesizable HDL design (SystemVerilog)
• Designed for ASIC & FPGA

Deliverables

• System Verilog RTL source code, testbenches, simulation and synthesis scripts, documentation (design specification, release notes, integration manual, verification specification)