Lithography / Nanopatterning

Semiconductor Process Services

Semiconductor Process Services

200 mm Lithography Services

Semiconductor Process Services

300 mm Lithography Services

How to work with us

Fraunhofer IPMS - Your research partner

Lithography Services for 200 mm Wafers

High-Precision DUV & MEMS Lithography for Industrial Applications

© Fraunhofer IPMS
Lithography area in the 200 mm MEMS cleanroom at Fraunhofer IPMS.

Our lithography serves as the central link between design and the finished device. Using state-of-the-art equipment—most notably our deep ultraviolet (DUV) scanner with the highest resolution and excellent overlay accuracy—we pattern 200 mm wafers with high precision, from feasibility studies through to stable volume production. We have expertise in a wide range of photoresists, coating systems, and exposure processes, and tailor each process precisely to the requirements of your product. Using modern resist simulation, we can optimally design structural layouts and process windows even before the first wafer run. This is how we lay the foundation for reliable, highly integrated, and cost-effective micro- and nanotechnologies on the 200 mm platform.

 

Our Lithography Expertise at a Glance

  • Pattern formation on 200 mm wafers for microelectronics, sensor technology, microelectromechanical systems (MEMS), and optical applications
  • High-resolution DUV scanner lithography with excellent overlay for demanding applications
  • Systematic process development, optimization, and stabilization for external customer projects and internal product lines
  • Support throughout the entire development cycle: from initial prototypes to small-scale production on 200 mm wafers
  • High flexibility in layer systems, photoresists, and mask designs in the 200 mm format
  • Close integration with upstream and downstream process steps (deposition, dry and wet etching, chemical-mechanical polishing (CMP), metallization, characterization, and testing) 

Available Lithography Processes in Detail

Photoresists

Spin coating on a 200 mm wafer.

We offer a wide selection of positive, negative, and protective photoresists with a broad range of layer thicknesses. Starting with thin photoresist layers as thin as 300 nanometers for front-end and fine metallization structures, we can also reliably produce thick photoresist layers up to at least 8 micrometers for deep etching and MEMS structures. Various adhesion promoters and developers for specific applications are also available.

 

Spin coating as a standard process:

  • MEGAPOSIT SPR700 is a versatile multi-wavelength positive resist that can be used for a wide range of film thicknesses from 1 to 4 micrometers.
  • UV5 is a DUV positive resist for resolutions starting at 200 nanometers, suitable for layer thicknesses ranging from 0.7 to 1.2 micrometers.   
  • UV1100 is a DUV positive resist for high resolutions up to 110 nanometers, covering a layer thickness range of 0.3 to 0.6 micrometers.
  • AZ nLOF 2070 is an i-line negative resist for lift-off and high-temperature applications and is used at layer thicknesses of 5.5 to 8 micrometers.
  • SX AR-PC 5000 is also available as a spray coating with a film thickness ranging from 7 to 30 micrometers.
  • AR 10L-400 is a bottom anti-reflection coating (BARC) for DUV photoresists and can be applied with layer thicknesses ranging from 50 to 90 nanometers.

 

Spray coating for special applications:

  • AZ 4999 is a positive resist for challenging topographies such as deep trenches and can be applied with layer thicknesses ranging from 2.8 to 7.5 micrometers.
  • AZ nLOF 2070 is also available as a spray coating with layer thicknesses ranging from 2.8 to 7.5 micrometers.
  • SX AR-PC 5000 is also offered as a spray coating with layer thicknesses ranging from 7 to 30 micrometers.
  • CYCLOTENE 3022-46 bisbenzocyclobutene (BCB) is used as a dielectric insulation layer, e.g., for wafer bonding.

To improve the adhesion of photoresists, we use the adhesion promoters HMDS and AR 300-80. While HMDS is used for standard applications, AR 300-80 is specifically used on surfaces with poor adhesion properties, such as metal or SiO2.

We use AZ 726 MIF and AZ 2026 MIF as developers. Both developers are metal-ion-free and contain 2.38 percent TMAH. While AZ 726 MIF is used for standard applications, AZ 2026 MIF has a higher dark-side removal rate due to various surfactants and additives and is used, among other things, with thicker photoresists.

An Overview of Our Exposure Systems

DUV cluster in the 200 mm MEMS cleanroom at Fraunhofer IPMS.

With our three complementary exposure systems, we cover a broad spectrum ranging from the nanometer to the millimeter scale. Through the targeted combination of scanner and mask aligner processes, we ensure that both front-end and back-end requirements are optimally addressed. Depending on your needs, we offer the highest resolution and overlay accuracy, stable submicrometer lithography, as well as cost-effective and flexible solutions for special applications—the ideal combination for applications ranging from prototyping to mass production.

 

DUV scanner with KrF excimer laser (248 nm wavelength)

Our DUV scanner is the solution for high-resolution, critical structures in the submicrometer range. It is designed for demanding high-end and ‘More-than-Moore’ technologies.

With a 248 nm wavelength, state-of-the-art projection optics, and resolution-enhancing techniques (RET), this system is particularly suitable for:

  • dense metal and contact layers
  • complex CMOS, mixed-signal, and sensor structures
  • applications with high requirements for resolution, overlay, and process stability

Specifications:

  • 1:4 projection exposure
  • Lens NA: 0.82
  • Resolution: ≤ 110 nm (lines/spaces), ≤ 150 nm (contact holes)
  • Field of view: 26 mm × 33 mm
  • Single-machine overlay (3σ): ≤ 4 nm

 

I-line stepper with mercury vapor lamp (365 nm wavelength)

The I-line stepper is our production platform for mature technologies with an excellent cost-benefit ratio. It is therefore the first choice for robust, long-lasting technologies at industrial volumes.

With a 365 nm wavelength, it offers:

  • Stable lithography for feature sizes in the classic submicrometer and micrometer range
  • High overlay accuracy for multilayer processes
  • Ideal conditions for analog/RF circuits, power electronics, sensor technology, and LEDs

Specifications:

  • 1:5 projection exposure
  • Resolution: ≤ 350 nm (lines/spaces)
  • Image field size: 22 mm × 22 mm
  • Single-machine overlay (3σ): ≤ 40 nm

 

Mask aligner with mercury vapor lamp (broadband exposure or with i-line filter)

Our mask aligner enables highly adaptable microfabrication. With the option of contact or proximity exposure, it is ideally suited for research and development (R&D), rapid prototyping, and specialized niche applications.

  • Broadband exposure (g-, h-, and i-line) enables:
  • Reliable imaging of thick photoresists and high topographies
  • Structure sizes ranging from a few micrometers to several millimeters
  • Ideal processes for MEMS and optical applications

Specifications:

  • 1:1 direct exposure
  • Wafer thickness: > 400 µm
  • Resolution: ≤ 3.5 µm (lines/spaces)
  • Overlay: ≤ 1 µm
  • Alignment methods: Top Side Alignment (TSA), Bottom Side Alignment (BSA), and IR alignment
  • Proximity, soft contact, and hard contact exposure depending on resolution requirements

Mask Data Preparation (MDP)

The MDP-Workflow at Fraunhofer IPMS.

Our Mask Data Preparation (MDP) bridges the gap between your circuit design and the finished photomask. We translate your layout data into finished mask data, tailored to the lithography process, mask manufacturer, and production requirements.

 

Our MDP Services

We support you throughout the entire process, from the initial design to the finished mask. This includes:

  • Layer mapping and derivation: Conversion of your design layers into lithographic layers, including Boolean operations and sizing, among other things, as needed
  • Tonal range: Derived from photoresist type and process requirements and implemented in the mask data set
  • Mask layout: Creation of the complete layout with dies, scribe lines, and frame, including barcodes, mask labels, and required alignment, control, and metrology structures in accordance with process and mask specifications
  • Format adaptation: Adaptation to mask format and exposure system (scaling, rotation, mirroring)
  • Data verification: Consistency and plausibility checks prior to release
  • Documentation: Complete mask documentation, including relevant information for lithography
  • Delivery: Mask data (GDSII/OASIS), delivered directly to the mask manufacturer upon mask procurement

 

Your Benefits

  • Reliable conversion of your design layout into mask data that can be transferred directly to the mask manufacturer
  • MDP in close coordination with our lithography specialists for process-optimized mask data
  • Fewer iterations with the mask manufacturer thanks to complete mask data
  • Flexibility for special masks, multilayer masks, and customer-specific photomask layouts

 

Resist Simulation

Schematic of resist simulation.

We offer high-quality resist simulations for the design and optimization of lithography processes. To do this, we use the modular LAB software from GenISys, which allows us to simulate both 2D topographic maps and 3D intensity distributions in the photoresist, as well as the resulting resist profiles after development. By systematically varying process parameters—such as exposure dose, focus, and the thicknesses of the resist and anti-reflection coating (ARC) layers—we determine process windows, optimal process parameters, and layer thicknesses before conducting initial trials on the production line. We are happy to support you from the feasibility study through to process-oriented model calibration.

 

Our Range of Services

Mask and layout definition:

  • Import of common layout formats such as GDSII and OASIS
  • Modeling of corner roundings
  • Use of gray-tone and phase-shift masks

Stack definition:

  • Definition of substrates and layers from a material database or as customer-specific entries
  • Incorporation of anti-reflection coatings (ARC)
  • Photoresist models with wavelength-dependent n/k data, bleaching parameters, Dill parameters, and development models (Mack4, CAR, Threshold)

Projection exposure:

  • Accounting for the source spectrum and mapping of various source shapes (e.g., circular, annular, quadrupole, dipole)
  • Modeling of the projection optics, including aberrations

Resist development and resist model calibration:

  • Threshold, Mack4 models, and CAR models (dynamic acid/quencher diffusion and reaction)
  • Coating development models with development rate tables   
  • Calibration of coating models using customer measurement data

Analysis and key metrics:

  • CD, NILS, contrast, cross-section, sidewall angle, standing waves
  • Best Focus, Depth of Focus (DOF), Dose to Size, Focus Exposure Matrix (FEM), Process Window (PW), Mask Error Enhancement Factor (MEEF)
  • Reflectivity, swing curves for optimizing resist and ARC thicknesses
  • Parametric optimization:
  • Optimization of process parameters (flow parameters) to achieve defined target CDs or process windows
  • Optical Proximity Correction (OPC):
  • Rule-based OPC
  • Model-based OPC for limited layout areas to improve imaging fidelity

 

Your Benefits

  • Faster and more cost-effective process development through significantly fewer wafer loops and iteration cycles until stable production is achieved
  • Reduced process risk through simulation of photoresist behavior across the entire process chain (exposure, post-exposure bake (PEB), development) and validated process windows on 200 mm wafers
  • Higher imaging fidelity and yield through targeted OPC and optimization of resist and ARC layer stacks

Metrology and Quality Assurance

© Fraunhofer IPMS
Microscope inspection of a wafer.

We ensure process stability and structural integrity in lithography through comprehensive metrology and quality assurance throughout the entire process chain—from mask exposure to PEB and development.

Using modern measurement techniques, we detect CD variations, overlay deviations, layer thicknesses, and defects, and derive concrete measures for process optimization from these findings.

 

What we measure and analyze

  • Critical Dimensions (CD): Precise measurement of isolated and dense structures such as lines, trenches, contact holes, pillars, etc.
  • Overlay: Exact determination of the alignment of structural layers, combined with stepper- or scanner-based overlay optimization for tight tolerances
  • Profile and topography measurements: Analysis of photoresist profiles, edge steepness, step heights, and surface roughness
  • Coating thicknesses and optical parameters: Characterization of photoresists, ARC, and hard mask layers (thickness, n/k)
  • Defect inspection: Detection and classification of defects in the lithography process or in subsequent process steps

 

Quality Assurance

  • Development and maintenance of measurement and testing concepts for lithography processes
  • Regular process and equipment monitoring to ensure stable production
  • SPC analyses (Statistical Process Control: control charts, trend analyses, process capability Cp/Cpk)
  • Standardized qualification and approval of new processes, mask sets, and materials
  • Regular calibrations traceable to national standards (e.g., PTB, NIST)

 

Your Benefits

  • Stable, controlled lithography processes through early detection and correction of deviations
  • High yields through data-driven process optimization
  • Demonstrable quality to customers through documented measurement and testing concepts

Lithography Services for 300 mm Wafers

Nanopatterning / E-Beam Lithography

© Fraunhofer IPMS
E-Beam Lithography area in 300 mm CMOS Clearoom at Fraunhofer IPMS.
© Fraunhofer IPMS
TEL Etch tool in 300 mm CMOS Clearoom at Fraunhofer IPMS.

Creating nano-scale structures is crucial for a wide range of applications in the semiconductor business. Key challenges are creating precisely controlled patterns with small dimensions, flexible and adaptable layout generation and processes as well as uniform and reproducible wafer-scale integration.

Fraunhofer IPMS offers state-of-the-art nanopatterning capabilities using electron beam direct write lithography and reactive ion etching. Thus, customized structures with sizes below 40 nm can be created on a variety of wafer sizes and substrate types. Starting from the customer’s design the whole package involving layout generation and modification, data preparation, e-beam lithography, pattern transfer using etch processes together with the in-line metrology and analytics up to dicing into single chips is offered.

 

Application examples

  • Fabrication of test structures for technology development
  • Structuring of Application Specific Integrated Circuits (ASICS)
  • Design tests of innovative devices and cell concepts and their variation on a wafer (Chip Shuttle)
  • Calibration pattern for metrology development
  • MEMS and NEMS patterning with productive quality
  • “Mix & Match” with optical exposure techniques

E-Beam Lithography for Sub-80 nm Structures in Quantum Computing CMOS Fabrication

© Fraunhofer IPMS
Parameters of the process stability on 300 mm wafers - pattern fidelity, uniformity and wafer to wafer reproducibility. Distribution of a 100 nm trench width with pitch 1/1 measured with CD-SEM over the 300 mm wafer

Universal quantum computers promise the possibility of solving certain computational problems significantly faster than classically possible. For relevant problems, millions of qubits are needed, which is only feasible with industrial production methods. This study presents an electron beam patterning process of gate electrodes for Si/SiGe electron spin qubits, which is compatible with modern CMOS semiconductor manufacturing. Using a pCAR e-beam resist, a process window is determined in which structure sizes of 50 nm line and 30 nm space can be reproducibly fabricated with reasonable throughput. Based on electrostatic simulations, we implemented a feedback loop to investigate the functionality of the gate electrode geometry under fabrication-induced variations.

Our Equipment:

 

Fraunhofer IPMS

200 mm MEMS Cleanroom Infrastructure

 

Fraunhofer IPMS

300 mm CMOS Cleanroom Infrastructure

 

Fraunhofer IPMS

Analytics, Metrology and Characterization