Ultra-Low Power Sustainable Spin Chips

Energy efficiency is the single greatest bottleneck in modern digital transformation. As AI and IoT applications expand exponentially, existing hardware architectures face critical power limitations. The European SPIN-CHIP project introduces a paradigm shift by leveraging spintronics to deliver highly sustainable, energy-efficient semiconductor solutions.

At Fraunhofer IPMS, we are bridging the gap between laboratory research and industrial fabrication by solving the critical challenges of spintronic integration.

What is the SPIN-CHIP project?

The SPIN-CHIP project is a European microelectronics initiative focused on developing ultra-low power, sustainable spintronic chips. By utilizing Magnetic Tunnel Junction (MTJ) technology, the project aims to advance EU technological sovereignty with energy-efficient hardware for AI, IoT, space, and medical applications.

How does Fraunhofer IPMS contribute to SPIN-CHIP?

Fraunhofer IPMS leads the integration challenge within the SPIN-CHIP consortium. The institute focuses on the monolithic integration of spintronic devices onto standard silicon platforms (CMOS) and establishes critical connections to future CHIPS JU Pilot Lines

The core innovation of SPIN-CHIP relies on a single spintronic component, the Magnetic Tunnel Junction (MTJ), optimized for four distinct application domains:

• Memory MTJs (MRAM for Space) Optimizing Non-Volatile Magnetoresistive RAM (MRAM) for high density and radiation hardness, securing independent European memory blocks for harsh space environments.
• Stochastic MTJs (AI & Security) Utilizing controllable random signals to natively power hardware-based AI accelerators, Universal Random Bit Samplers (URBS), and Physical Unclonable Functions (PUF) for hardware-level security.
• Sensing MTJs (Ultra-Sensitive Medical Tech) Developing room-temperature magnetic field sensors capable of picotesla-level (pT) sensitivity, removing the need for expensive cryogenic cooling in advanced cardiac monitoring.
• RF MTJs (Energy-Autonomous Communication) Harnessing steady-state magnetization oscillations for direct signal processing, RF energy harvesting, and low-power wake-up receivers.

The consortium targets specific, measurable advancements to validate spintronics as a viable industrial standard:

• Monolithic CMOS Integration: Successful fabrication of hybrid MTJ/CMOS chips at both 22 nm and 180 nm nodes.
• Multi-Functional Modules: Combining sensing, memory, and computing blocks into single, versatile spintronic components.
• 86% RF Power Reduction: Lowering the power consumption of critical RF communication devices from 7W to 1W, turning bulky equipment into handheld devices.
• Space-Ready Efficiency: Achieving a two-fold energy consumption reduction for MRAM buffer memories used in space electronics.
• Ultra-Low Standby Power: Dropping standby power consumption below 100 mW using smart wake-up receivers.

Coordinated by Thales TRT (France), the SPIN-CHIP project connects leading European Research and Technology Organizations (RTOs), universities, and semiconductor industry leaders to secure an autonomous European value chain.

Fraunhofer IPMS collaborates closely with German and international partners—including Infineon Technologies AG, Singulus Technologies AG, and 3D-Micromac AG—to drive monolithic integration tasks and bridge developments directly with future CHIPS JU Pilot Lines.

Why is spintronics important for the future of EU microelectronics?

Spintronics manipulates the intrinsic spin of electrons alongside their electrical charge. This allows devices like MTJs to retain data without continuous power supply, drastically cutting down energy consumption, minimizing area occupancy, and boosting processing speeds in next-generation edge devices.

What is the difference between monolithic and heterogeneous integration in chip design?

Monolithic integration involves building the spintronic components directly onto a single, common silicon CMOS platform, which optimizes performance and footprint. Heterogeneous integration combines separate functional blocks (chiplets) onto a single substrate. SPIN-CHIP utilizes both approaches to maximize compatibility with modern chiplet standards.

• France: CEA, CNRS, IC’ALPS, NanoXplore, Thales Alenia Space
• Belgium: IMEC, MAGICS, Université Catholique de Louvain, Vertical Compute SRL
• Germany: Fraunhofer IPMS, Infineon Technologies AG, Singulus Technologies AG, 3D-Micromac AG
• Italy: MARIS scrl, Politecnico di Bari, Università della Calabria, Università degli Studi di Messina
• Netherlands: OPT-NET, Radboud University
• Portugal: Cardioid Technologies LDA, Beyond Vision, INESC Microsistemas e Nanotecnologias, International Iberian Nanotechnology Laboratory
• Sweden: NanOsc AB, Project Management in Research Rosqvist & Widforss AB, Göteborgs Universitet
• Cyprus: SignalGenerix Limited