RISC-V processor core for functional safety

Whitepaper #7: RISC-V processor core for functional safety

Fraunhofer IPMS

Together with industrial partners, the University of California, Berkeley has developed the „Reduced Instruction Set Computer V“ (RISC-V) using an open instruction set architecture (ISA). The goal of the project was to make it possible to use future processors for a wide range of applications. Contrary to many other instruction set architectures, RISC-V is freely available as an open source license, making it possible for anyone to develop and market RISC-V cores and processors without having to pay any licensing fees for doing so.

The corresponding specifications are being coordinated by the RISC-V Foundation based in Switzerland and founded in 2015. An important development goal of the open ISA was to facilitate the development of fast, small, high-performance and energy-efficient processors. Implementation is possible both on FPGAs and ASICs. The three available integer-based ISAs are primarily distinguished by bit width. As the name suggests, the architect versions RV32I, RV64I and RV128I have a width of 32, 64 and 128 bit respectively. In addition, RV32E also exists with only 16 registers, a version specially designed for embedded systems.

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RISC-V processor core for functional safety

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