Time Sensitive Networking IP-Cores
Fraunhofer IPMS develops Time Sensitive Networking IP Cores for deterministic and time-synchronised data transmission in Ethernet networks. Time Sensitive Networking, TSN for short, is a term for a series of standards that were initially developed by the IEEE Ethernet AVB (Audio Video Bridging) Task Force. These standards extend Ethernet networks by the possibility of time synchronisation and deterministic data transmission. Time-critical data streams can thus be transported with guaranteed latency through an Ethernet TSN network without having to use real-time capable fieldbus systems or special hardware. The Time Sensitive Networking IP Core designs developed by Fraunhofer IPMS facilitate the integration of TSN into devices that are to be used in an Ethernet TSN network. The IP cores are silicon proven for ASIC technologies up to 22nm or can be integrated into FPGA designs.
Available TSN IP-Cores
- Time Sensitive Networking Endpoint Core – TSN-EP
- Time Sensitive Networking Switched Endpoint Core – TSN-SE
- TSN Multiport Switch Core - TSN-SW