Time Sensitive Networking IP-Cores

Time Sensitive Networking IP-Cores

TSN IP Cores for Ethernet Networks

Fraunhofer IPMS develops Time Sensitive Networking IP Cores for deterministic and time-synchronised data transmission in Ethernet networks. Time Sensitive Networking, TSN for short, is a term for a series of standards that were initially developed by the IEEE Ethernet AVB (Audio Video Bridging) Task Force. These standards extend Ethernet networks by the possibility of time synchronisation and deterministic data transmission. Time-critical data streams can thus be transported with guaranteed latency through an Ethernet TSN network without having to use real-time capable fieldbus systems or special hardware. The Time Sensitive Networking IP Core designs developed by Fraunhofer IPMS facilitate the integration of TSN into devices that are to be used in an Ethernet TSN network. The IP cores are silicon proven for ASIC technologies up to 22nm or can be integrated into FPGA designs.

 

Key Features:

  • Time synchronisation (IEEE 802.1 AS-2020)
  • Traffic-Shaping (IEEE 802.1 Qav und Qbv)
  • Frame Preemption (IEEE 802.3br und IEEE 802.1Qbu)
  • Frame Replication and Elimination (IEEE 802.1CB)
  • SRP Enhancements (IEEE 802.1Qcc)
  • Stream Filtering and Policing (IEEE 802.1Qci)
  • Cyclic Queuing and Forwarding (IEEE 802.1Qch)
  • Ethernet-MAC-Kommunikation (IEEE 802.3)

 

Available Time Sensitive Networking Cores:

  • TSN-EP - TSN Endpoint Core for endpoint devices
  • TSN-SE - TSN Switched Endpoint Core for switched endpoint devices (2-port)
  • TSN-SW - TSN Multiport Switch Core - for Multiport Switches

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