CAN IP-Core Design
Fraunhofer IPMS offers a CAN IP core design for serial communication for its application in FPGA or ASIC. The CAN core is a bus controller that performs serial communication according to the CAN 2.0B, CAN FD specification according to ISO 11898-1:2015 and CAN XL according to CiA 610-1. The core is certified as ASIL-D-ready according to ISO26262 for functional safety in automotive applications. The IP design can be integrated into devices that use CAN or higher layer CAN-based communication protocols and is silicon proven for ASIC technologies up to 22nm. The CAN core is extensively verified and proven in plugfests and a wide range of production designs.
- Support of CAN, CAN FD and CAN XL
- FIFO or priority mode
- Programmable data and baud rates
- Programmable interrupts
- Loopback mode for self-testing
- ISO-26262 ASIL-D ready