Fraunhofer Institute for Photonic Microsystems
Fraunhofer Institute for Photonic Microsystems

Ethernet IP Cores

TSN, LLEMAC, MACsec

Ethernet IP Cores

Time Sensitive Network IP Core

Fraunhofer IPMS develops advanced Time-Sensitive Networking (TSN) IP cores that enable deterministic, low-latency, and time-synchronized data transmission over standard Ethernet networks. Designed for integration into both ASIC and FPGA architectures, our silicon-proven TSN IP cores are ideal for use in real-time industrial communication systems.

TSN is a set of IEEE 802.1 standards, originally initiated by the Ethernet AVB (Audio Video Bridging) Task Force, that transforms conventional Ethernet into a deterministic communication technology. With TSN, time-critical data streams can be transmitted with guaranteed latency and precision timing, eliminating the need for dedicated real-time fieldbus systems or proprietary communication hardware.

 

Advantages of Fraunhofer TSN IP Cores

  • Ultra-low latency cut-through architecture for real-time performance
  • Precision time synchronization with IEEE 802.1AS-2020 (gPTP) achieving nanosecond accuracy
  • Standards-based traffic shaping per IEEE 802.1Qav and 802.1Qbv
  • Integrated LLEMAC for efficient media access control
  • Flexible Ethernet speeds: 10/100/1000 Mbps, with 10G support under development

Our TSN IP cores are optimized for high reliability, ease of integration, and long-term scalability, making them the ideal solution for industrial automation, automotive Ethernet, robotics, energy systems, and telecommunication networks requiring guaranteed quality of service (QoS) and real-time data delivery.

Technical Specifications

© Fraunhofer IPMS
IP Core for TSN Mulitport Switches – TSN-SW

IP Core for TSN Mulitport Switches – TSN-SW

Engineered for deterministic industrial Ethernet, this TSN multiport switch delivers precise timing and predictable performance for factory automation, robotics, and energy systems. It combines ultra‑low‑latency cut‑through forwarding with standards‑based TSN, scalable port counts, and robust software support for fast, reliable integration.

Features

  • Scalable port density: up to 24 external ports + 1 host port (variants from 2 external + 1 internal)
  • Ultra‑low‑latency cut‑through switching for time‑critical traffic
  • Up to 8 traffic classes with IEEE 802.1Qav credit‑based shaping and 802.1Qbv time‑aware scheduling
  • IEEE 802.1AS‑2020 time sync, grandmaster‑capable with nanosecond‑level accuracy
  • 802.1Q VLAN tagging with configurable VLAN‑PCP to TSN‑queue mapping (QoS by PCP)
  • Integrated triple‑speed low‑latency Ethernet MAC; 10/100/1000 Mb/s
  • Flexible interfaces: Host (AXI, Avalon ST/MM, APB) and PHY (MII, GMII, RGMII)
  • Software package: FreeRTOS driver/HAL, PTP/AS‑2020, CLI, and example projects

Product Sheet: TSN-SW for Multiport Switches

IP Core for TSN Switched Endpoint – TSN-SE

Designed for deterministic industrial Ethernet devices, this TSN switched endport delivers precise timing and predictable performance for motion control, robotics, and machine networking, combining ultra‑low‑latency forwarding with standards‑based TSN and streamlined software integration.

Features

  • Ultra‑low‑latency cut‑through switching for time‑critical traffic
  • Up to 8 traffic classes with IEEE 802.1Qav credit‑based shaping and 802.1Qbv time‑aware scheduling
  • IEEE 802.1AS‑2020 time sync, grandmaster‑capable with nanosecond‑level accuracy
  • 2 external + 1 internal port for flexible endpoint/topology integration
  • 802.1Q VLAN tagging with configurable VLAN‑PCP to TSN‑queue mapping (QoS by PCP)
  • Integrated triple‑speed low‑latency Ethernet MAC; 10/100/1000 Mb/s
  • Flexible interfaces: Host (AXI, Avalon ST/MM, APB) and PHY (MII, GMII, RGMII)
  • Software package: FreeRTOS Driver/HAL, PTP/AS‑2020, CLI, and example projects

Product Sheet: TSN-SE for Switched Endpoint Devices

© Fraunhofer IPMS
IP Core for TSN Switched Endpoint – TSN-SE
© Fraunhofer IPMS
IP Core for TSN Endpoint – TSN-EP

IP Core for TSN Endpoint – TSN-EP

 

Built for deterministic industrial Ethernet endpoints, this TSN-enabled device delivers precise timing and predictable performance for motion control, robotics, and smart sensors, with ultra-low latency and standards-based TSN for easy integration.

Features

  • Ultra-low-latency cut-through switching for time-critical cycles
  • Up to 8 traffic classes with IEEE 802.1Qav credit-based shaping and 802.1Qbv time-aware scheduling
  • IEEE 802.1AS-2020 time sync, grandmaster-capable with nanosecond-level accuracy
  • 1 external + 1 internal port for compact endpoint/topology integration
  • Integrated triple-speed low-latency Ethernet MAC; 10/100/1000 Mb/s
  • Flexible interfaces: Host (AXI, Avalon ST/MM, APB) and PHY (MII, GMII, RGMII)
  • Software package: FreeRTOS Driver/HAL, PTP/AS-2020, CLI, and example projects

Product Sheet: TSN-EP for Endpoint Devices

Evaluation Kits

© Fraunhofer IPMS
TSN Netleap Evaluation Kit

TSN Netleap Evaluation Kit 

  • Altera based FPGA-Board
  • SD-Card with image
  • Power supply 5V/2A
  • Two-part housing
  • USB-PPS-Cable
  • User Guide

This kit comprises both harware and IP Core.

© Fraunhofer IPMS
TSN Xilinx ZCU102 Evaluation Kit

TSN Xilinx ZCU102 Evaluation Kit

  • AMD Xilinx FPGA-Board ZCU102
  • SD-Card with image
  • Power supply
  • 2 micro USB cable
  • USB hub
  • Ethernet cable
  • SFP adapter (SW: 4, SE: 2, EP: 1)
  • User Guide

This kit comprises both harware and IP Core.

© Fraunhofer IPMS
TSN Evaluation Bit File (for Xilinx ZCU102 or Netleap Board)

TSN Evaluation Bit File (for Xilinx ZCU102 or Netleap Board)

  • FreeRTOS Driver/HAL
  • FreeRTOS PTP/AS-2020
  • FreeRTOS Command Line Interface
  • 802.1Q VLAN Switch functionality (SE, SW)
  • Optional Free RTOS Qci
  • Optional FreeRTOS Qcc
  • Optional FreeRTOS IwIP integration
  • Optional TSN Linux Embedded Driver Reference Design

This kit consists only of the IP Core (no hardware).

Downloads

Low Latency Ethernet MAC (LLEMAC) IP Core

The IP design implements an Ethernet Media Access Controller (MAC) that is compatible with IEEE 802.3 and IEEE 802.3-2002 specifications at 10/100 Mbps and 1 Gbps. With its extremely low input and output latency, the Low Latency Ethernet MAC Core is ideal for implementation in TSN Ethernet nodes and other devices that require low latency when receiving and sending Ethernet frames. The core is certified as ASIL-D-ready according to ISO 26262 for functional safety in automotive applications.

Features

  • IEEE 802.3 compliant, triple‑speed Ethernet MAC (10/100/1000 Mbps)
  • TSN-ready: enables high‑precision time synchronization
  • Deterministic low latency: 10-cycle TX, 6-cycle RX
  • Jumbo frame support for higher throughput
  • Full/half‑duplex point‑to‑point operation
  • 10BASE‑T1S support (single‑pair Ethernet)
  • Broad PHY connectivity: MII (10/100), GMII (1G), RGMII (10/100/1000)
  • MDIO interface for PHY configuration and management
© Fraunhofer IPMS
Low Latency Ethernet MAC (LLEMAC) IP Core

Downloads

MACsec IP Core

The MACsec IP Core supports highest data rates and implements IEEE 802.1AE-2018 Layer 2 security standard for authentication, confidentiality, and integrity between LAN hosts. MACsec permits authorized nodes to communicate, encrypts transmitted data for confidentiality, and provides cryptographic mechanisms to ensure data integrity. It is compatible with the Fraunhofer IPMS LLEMAC IP core, any other Ethernet MAC IP core, or can operate as a standalone solution.

The MACsec IP core can be provided platform-independently for all FPGA platforms and any foundry technology. Fraunhofer IPMS also offers services to extend IP cores as well as to develop complete customer specific subsystems. 

Fraunhofer IPMS has more than 20 years of experience in the development and licensing of IP cores and several hundreds of users worldwide. Most customers are from the automotive, aerospace and manufacturing industries.

Features

  • Compliance with IEEE Std 802.1AE-2018
  • Supports authentication and authenticated encryption
  • Speeds from 10M to 50G, >50G via parallel pipelines on-request
  • Supports NIST encryption standards (US)
  • Key width: 128 & 256 bits (supports AES-GCM and AES-GCM-XPN)
  • VLAN-in-Clear
  • Full duplex or Half duplex architecture
  • Secure Channel support up to 216
  • Detailed statistics and error reporting
  • AXI stream interface for MAC data
  • Different host controller interfaces for configuration (APB, AHB, …)
  • Additional user specific sideband information
  • Configurable Header Prefix
  • Fully synchronous and synthesizable HDL design (SystemVerilog)
  • Designed for ASIC & FPGA

Deliverables

  • System Verilog RTL source code, testbenches, simulation and synthesis scripts, documentation (design specification, release notes, integration manual, verification specification) 
© Fraunhofer IPMS
MACsec IP Core

Downloads

Applications for Ethernet IP Cores

In applications where precise timing and guaranteed delivery are critical, our Time-Sensitive Networking (TSN) Ethernet IP cores enable deterministic, low-latency, and time-synchronized data communication over standard Ethernet. Designed for ASIC and FPGA integration, our silicon-proven IP cores bring real-time reliability to industrial automation, robotics, automotive, energy, and telecom systems, where every microsecond counts.

Automotive

TSN IP cores enable real-time, deterministic Ethernet communication for advanced driver-assistance systems (ADAS), in-vehicle networking, and autonomous driving, ensuring synchronized data exchange across ECUs with guaranteed latency.

Naval

TSN technology supports secure, real-time communication for shipboard control systems, navigation, and sensor networks, ensuring robust performance even under harsh maritime conditions and EMI exposure.

Space

For spacecraft systems and satellite payloads, TSN IP cores enable reliable, low-latency data exchange with deterministic timing, supporting mission-critical communication in weight- and power-constrained environments.

Telecommunication

TSN ensures precise timing and traffic management across telecom networks, supporting 5G fronthaul, edge computing, and virtualized network functions with deterministic data delivery.

Industrial automation

In industrial automation and robotics, TSN replaces legacy fieldbus systems with Ethernet-based real-time networking, enabling synchronized motion control, predictive maintenance, and scalable Industry 4.0 architectures.

Energy

For smart grids and substation automation, TSN enables secure, real-time communication with precise synchronization between distributed control systems, improving grid stability and response times.

Defense

TSN provides rugged, secure Ethernet communication with guaranteed timing for defense platforms, enabling seamless integration of mission systems, sensors, and controls in dynamic and high-interference environments.

Aerospace

In avionics and flight control systems, TSN delivers time-critical data with nanosecond precision over lightweight Ethernet, reducing cabling complexity while meeting strict safety and synchronization requirements.

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