RISC-V EMSA5 IP Cores

Fraunhofer IPMS offers a highly configurable processor IP core based on the open-standard RISC-V architecture. The EMSA5-GP IP core enables the development of application-specific RISC-V processors, offering an efficient and scalable solution for deeply embedded systems, edge computing, IoT devices, and edge AI applications. 

Supported by multiple industry-standard Integrated Development Environments (IDEs), the EMSA5-GP allows for fast, professional software development and easy integration into complete system designs.

Fraunhofer IPMS provides the RISC-V EMSA5-GP IP core as a platform-independent solution, suitable for a wide range of FPGA platforms and custom ASIC implementations across various foundry technologies. The processor core can also be extended with customer-specific modules, and Fraunhofer IPMS supports the development of complete subsystems tailored to specific application requirements.

With over 20 years of experience in IP core development and licensing, Fraunhofer IPMS has supplied its processor IP to hundreds of global users. Our RISC-V IP cores are widely deployed in automotive, aerospace, and industrial automation sectors where reliability, configurability, and long-term availability are essential.

Features

• 32-bit RISC-V core with 5-stage pipeline; low footprint and high frequency
• ISA support: RV32I and RV32E
• Privileged modes: Machine (M) and User/Application (U)
• Physical Memory Protection (PMP)
• Hardware trigger module and performance counters
• RISC-V-compliant debug interface
• Aditional standard package: APB QSPI, APB PLIC, AHB-Lite single-layer interconnect (SLIC), AHB-Lite to APB bridge

Product Sheet: EMSA5-GP – RISC-V Processor IP Core

Fraunhofer IPMS offers a RISC-V-based processor IP core specifically designed for functional safety applications. The EMSA5-FS IP core is ASIL-D ready, certified in accordance with ISO 26262:2018, making it ideal for safety-critical automotive systems. It also supports compliance with IEC 61508, making it suitable for industrial safety applications as well.

The EMSA5-FS is supported by multiple integrated development environments (IDEs), enabling efficient and professional system-level software development under functional safety requirements.

This RISC-V IP core is platform-independent and can be deployed on various FPGA platforms or integrated into customer-specific ASIC designs across all major foundry technologies. Fraunhofer IPMS also offers custom module extensions and the development of complete subsystems, ensuring that the processor core fits seamlessly into your unique application environment.

With over 20 years of experience in the design and licensing of IP cores, Fraunhofer IPMS has earned the trust of hundreds of users worldwide, particularly in the automotive, aerospace, and industrial automation sectors. Our deep expertise ensures reliable, scalable, and standards-compliant processor IP solutions for the most demanding industries.

Features

• 32-bit RISC-V core with 5-stage pipeline; low footprint and high frequency
• ISA support: RV32I and RV32E
• Privileged modes: Machine (M) and User/Application (U)
• Physical Memory Protection (PMP)
• Hardware trigger module and performance counters
• RISC-V–compliant debug interface
• Functional safety: dual-mode/triple-mode redundancy, dual-mode lockstep, safety manager, safety watchdog
• Aditional standard package: APB QSPI, APB PLIC, AHB-Lite single-layer interconnect (SLIC), AHB-Lite to APB bridge
• Bus fabrics safety package: AHB bus ECC, AHB-Lite to APB bridge ECC, AHB-Lite multi-layer interconnect ECC

Product Sheet: EMSA5-FS – RISC-V Functional Safety Processor IP Core

The EMSA5 Demo Platform is an ideal tool for evaluating the RISC-V Processor IP Cores EMSA5-GP. It contains an Artix®-7 35T FPGA Arty evaluation board with an implemented EMSA5-IP core. Thanks to the included peripherals and expansion interfaces, the kit is ideal for numerous applications. The kit is programmable via JTAG and Quad-SPI-Flash and contains a JTAG port, 10/100 Mb/s Ethernet and a USB-UART bridge, four Pmod connections and an Arduino shield extension connection.

EMSA5-GP AI Support

EMSA5's MultiCore architecture enables efficient data processing on aggregating gateways, featuring optional hardware acceleration and compatibility with the TensorFlow Lite toolchain for implementing pre-trained models. For edge AI applications, EMSA5's low-power, compact RISC-V processors facilitate real-time data processing at the source node, ensuring optimal performance in resource-constrained environments.