RISC-V processor IP Core EMSA5
Fraunhofer IPMS offers a processor IP Core based on the RISC-V architecture. The open instruction set architecture (ISA) enables the development of highly application-optimized RISC processors. The EMSA5-GP is supported by several IDEs and thus enables efficient and professional software development for complete systems. The processor IP is suitable for deep embedded systems, edge computing, embedded IoT and edge AI.
The RISC-V IP core can be made available platform-independently for various FPGA platforms as well as integration into customer-specific ASIC developments for any foundry technologies. Fraunhofer IPMS also provides services to extend the processor core IP with customer-specific modules and provides complete subsystems.
Fraunhofer IPMS has more than 20 years of experience in the design and licensing of IP cores design and several hundreds of users worldwide - a majority is used in the automotive, aerospace and automation industries.
- 32-bit, 5-stage pipeline architecture
- Small footprint with high frequency
- RISC-V Extensions: E, C and M (configurable)
- Privileged Instructions: Machine (M) and User/Application (U) mode
- Physical memory protection (PMP)
- Hardware trigger module and performance counter
- RISC-V compatible debugger
- PLIC - Platform Level Interrupt Controller
- AHB-lite interface