ICICDT 2021 News
- Tutorials online
- Invited talks and keynote speaker updates
- Social program announced
- See "ICICDT 2021 Prorgram" tab for more
ICICDT 2021 will take place from September 15 to September 17, 2021 in a virtual format. It will be organized by Fraunhofer IPMS in Dresden, Germany.
The International Conference on IC Design and Technology (ICICDT) is the global forum for interaction and collaboration of IC design and technology for "accelerating product time-to-market". Close collaboration of the multi-discipline technical fields design / device / process accelerates the implementation of new designs and new technologies into manufacturing.
IC industry trends toward specializing system design and manufacturing outsourcing, such as fabless design house, wafer foundry, design automation tool/software house, and semiconductor processing tool supplier, created the needs for individuals with multi-discipline technical skills for collaborations. Furthermore, advanced IC technology no longer can offer the same level of control over many parameters that have direct adverse impact on circuit behavior. New IC designs also push the limit of technology, and in some cases require specific fine-tuning of certain process modules in manufacturing. Thus the traditionally separated communities of design and technology, design/device/process, are increasingly intertwined.
Issues that require close interaction and collaboration for trade-off and optimization by all design/device/process fields are addressed in this conference. They are:
As IC design and process technology continue to advance for increased performance, lower power, and accelerated time-to-market, the engineering activities, traditionally separated along the boundary of design and process technology, will have difficulties in meeting the shrinking window of product optimization tasks. ICICDT provides a forum for engineers, researchers, scientists, professors and students to cross this boundary through interactions of design and process technology on product development and manufacturing. The unique workshop style of the conference provides an opportunity to technologists and product designers to exchange breakthrough ideas and collaborate effectively. Two days of technical presentations and workshops will be preceded by a one-day tutorial program of value to both the expert and the beginner.
|Advisory Committee:||Prof. Stefano D’Amico|
|Conference Chair:||Bich-Yen Nguyen|
|Conference Co-Chair:||Dr. Wenke Weinreich|
|Technical Program Chair:||Prof. Hubert Lakner|
|Executive Chair:||Bich-Yen Nguyen & Thuy Dao|
|Keynote Chair:||Prof. Yuichiro Mitani|
|Local Arrangement Chair:||Dr. Wenke Weinreich|
|Tutorial Chair:||Prof. Harald Schenk & Prof. Koji Eriguchi|
|Exhibition Chair:||Tina Hoffmann|
|Publicity & Award Chair:||Dr. Kin P. Cheung|
|Publication Chair:||Prof. Chun Zhao|
|Treasurer:||Dr. Dina Triyoso|
|Secretary:||Prof. Wen Liu|
It is with great sadness that we convey to you the news that Prof. Cezhou Zhao, Professor in the Department of Electrical and Electronic Engineering of School of Advanced Technology, Xi'an Jiaotong-Liverpool University, and co-chair of ICICDT 2021, has passed away unexpectedly. Prof. Zhao was an inspiring leader and a strong voice within the School and much loved and respected by colleagues and students in the University. We at ICICDT are with his family and friends in our thoughts.
|Advanced transistor / Memory Devices / Advanced materials and technologies||Gong Xiao, Cuiqin Xu, Akif Sultan, Dina Triyoso, Ran Cheng|
|EDA & design optimization, DFM/DFT/DFR/DFY||Rouwaida Kanj, Yan Wang, Thomas Kämpfe|
|Advanced packaging, 2.5D/3D integration||Thuy Dao, Bich-Yen Nguyen, David Pan, Xin Lin, Thomas Werner, Guillaume Besnard|
|System-on-Chip (SoC) / Internet of Things /AI||Xuan-Tu Tran, Philippe Flattresse, Wenke Weinreich|
|Reliability||Kin Cheung, Yuichiro Mitani, Koji Eriguchi, Chun Zhao|
|RF/analog and mixed signal/ IO and ESD Protection / Low Power||Philippe Galy, Stefano D'Amico, Nima Shahpari|
To give you an idea of speakers and papers that have appeared at previous ICICDT conferences, please look into the program schedules from past ICICDT Conferences:
Ajda Omrani - mcc Agentur für Kommunikation
Dr. Wenke Weinreich - Fraunhofer IPMS (Center Nanoelectronic Technologies CNT)
The Fraunhofer Institute for Photonic Microsystems IPMS in Dresden is one of 74 institutes in Germany with a modern R&D infrastructure in the field of optical sensors and actuators, integrated circuits, microsystems (MEMS/MOEMS) and nanoelectronics. Fraunhofer IPMS is a worldwide leader in research and development services for electronic and photonic microsystems in the fields of Smart Industrial Solutions, Medical & Health applications and Improved Quality of Life. Innovative products can be found in all large markets – such as ICT, consumer products, automobile technology, semiconductor technology, measurement and medical technology – products which are based upon various technology developed at Fraunhofer IPMS.
We would have loved to welcome you in Dresden, the capital city of the German state of Saxony. Dresden has a long history as the capital and royal residence for the Electors and Kings of Saxony, who for centuries furnished the city with cultural and artistic splendor. The city was known as the Jewel Box, because of its baroque and rococo city centre. Today, Dresden is a cultural, educational and political centre of Germany and Europe. The Dresden University of Technology is one of the 10 largest universities in Germany. The economy of Dresden and its agglomeration is one of the most dynamic in Germany and ranks first in Saxony. It is dominated by high-tech branches, often called “Silicon Saxony”. Dresden is one of the most visited cities in Germany with 4.7 million overnight stays per year.
The conference ID is 51558X.
ICICDT 2021 allows only online submission of the papers in pdf format. Papers submitted for ICICDT 2021 must not exceed four pages with all illustrations and references included. The IEEE templateis available for download. Each paper should have 2-4 pages. Please format your paper according to the manuscript specifications.
Due to timing constraints associated with the paper review process, paper must be received by May 17th, 2021 (UPLOAD PAPER HERE). After selection of papers, authors will be informed of the decision of the Technical Program Committee by e-mail before June 21st, 2021. Soon after that, the preliminary program will be published here online.
Authors of accepted papers have to submit online the final camera-ready manuscript in PDF format and submit online the IEEE Copyright Form before July 15th, 2021. The working language for the conference is English, which will be used for all presentations and printed material.
Papers submitted for review must clearly state:
The degree to which the paper deals with these issues will affect whether the paper is selected. The most frequent cause of rejection of submitted papers is a lack of new results. Only work that has not been previously published at the time of the conference will be considered. Submission of a paper for review and subsequent acceptance is considered as an agreement that the work will not be placed in the public domain prior to the conference.
ICICDT 2021 allows only online submission of the papers in PDF format. Please strictly follow the guidelines in Author Information while preparing the paper.
It is MANDATORY to verify the PDF file of the paper for IEEE compliance before submission using PDF Express. Papers that are not IEEE compliant will not be included in the proceedings nor published on IEEE Xplore.
When checked with PDF Express the paper is NOT submitted yet. After receiving confirmation of compliance from PDF Express authors must submit the PDF file approved by PDF Express through the online submission system.
Please double check the informations that you provide during online submission:
Since these informations will be used unchanged in the conference program and proceedings, it is important that you enter them correctly. Please rember to submit online also the IEEE Copyright Form after submitting the final paper.
(is constantly updated, last update: June 3, 2021)
|Dr. Abu Sebastian
IBM Research (Zurich, Switzerland)
|"In-memory computing: The next frontier in deep learning acceleration?"|
|Dr. Chidi Chidambaram
Qualcomm (Albany, New York, US)
|"Semiconductor challenges in realizing the full benefit of 5G mmWave and extending the roadmap into 6G"|
|Dr. Mirko Sanzaro
Toshiba Europe / Cambridge Research Laboratory (UK)
|"A photonic integrated quantum communication system"|
|Dr. Alvin Leng Sun Loke
NXP Semiconductors (Eindhoven, Netherlands)
|"Advancing Automotive ICs into Advanced CMOS Nodes"|
"In-memory computing: The next frontier in deep learning acceleration?"
The rise of AI and in particular deep learning is a key driver for innovations in computing systems. There is a significant effort towards the design of custom ASICs based on reduced precision arithmetic and highly optimized dataflow. However, the need to shuttle millions of synaptic weight values between the memory and processing units, remains unaddressed. In-memory computing (IMC) is an emerging computing paradigm that addresses this challenge of processor-memory dichotomy. Attributes such as synaptic efficacy and plasticity can be implemented in place by exploiting the physical attributes of memory devices such as phase-change memory (PCM). It is shown that, using custom “additive noise training”, software equivalent accuracy deep learning inference is possible. Moreover, using a mixed-precision training approach, iso-accuracy training is also possible. The IMC approach can be easily extended to spiking neural networks and to also implement additional entities such as explicit associative memory in an efficient manner for memory augmented neural networks. I will also present deep learning demonstrations based on a first of its kind IMC compute core based on PCM integrated in 14nm CMOS technology. Finally, I will provide a brief overview of photonic in-memory computing that could facilitate unprecedented latency and compute density.
"Semiconductor challenges in realizing the full benefit of 5G mmWave and extending the roadmap into 6G"
Chidi Chidambaram leads the process technology and foundry engineering team at Qualcomm as Vice President Engineering. Qualcomm is a leader among the fab less industry in bringing leading edge semiconductor technologies to manufacturing - Qualcomm was the first company to ship large volume products in 10 nm technology in 2017. Chidi’s team is also responsible for RF devices based on finlet and SOI transistors. Earlier Chidi developed silicon technology at Texas Instruments and was instrumental in the first embedded SiGe implementation by semiconductor Industry. Chidi is recognized as a IEEE fellow for contribution to strain engineering and Design technology co-optimization (DTCO). Chidi’s 20+ year semiconductor career has evenly straddled research and development with over 60 each of refereed articles and patents.
"A photonic integrated quantum communication system"
Mirko Sanzaro was born in Avola, Italy, in 1988. He received the M.Sc. degree (summa cum laude) in Electronic Engineering and the Ph.D. degree ( summa cum laude) in Information Technology Engineering from Politecnico di Milano, Milan, Italy, in 2013 and 2017, respectively. He is a currently a Research Scientist at Toshiba Europe Limited. His research interests include the design, development, and characterization of Quantum Key Distribution instrumentation.
"Advancing Automotive ICs into Advanced CMOS Nodes"
Alvin Loke is a Technical Director at NXP Semiconductors in San Diego, having worked on every CMOS node spanning from 250nm to 2nm at Agilent, AMD, Qualcomm, and TSMC. He received a B.A.Sc. degree with highest honors in engineering physics from the University of British Columbia, and M.S. and Ph.D. degrees in electrical engineering from Stanford University. Upon graduating, he spent several years in CMOS process integration. Since 2001, he has worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interfacing, and analog design methodologies. He has been an active volunteer in the IEEE Solid-State Circuits Society (SSCS) since 2003, having served as Distinguished Lecturer, Webinar Chair, CICC Committee Member, Denver and San Diego Chapter Chair (both of which received Outstanding Chapter Awards under his leadership), and Guest Editor for Journal of Solid-State Circuits and Solid-State Circuits Letters. He currently serves as a SSCS AdCom Member and Chapters Chair as well as a VLSI Symposia Committee Member. Alvin has presented many invited talks, including short courses at ISSCC, VLSI Symposia, CICC, and BCICTS. He has authored over 60 publications (including the CICC 2018 Best Paper) and 28 US patents.
|Dr. Sabine Kolodinski
Globalfoundries (Dresden, Germany)
|"IC Design & Technology Co-Development: e-NVM & mmWave enablement of 22FDX"|
|Prof. Peide Ye
Purdue University (Indiana, US)
|“Dynamic Studies of Polarization Switch in Ferroelectric HfZrO2"|
|Prof. Jane Li
University of Pennsylvania (Philadelphia, US)
|"Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications"|
|Prof. Hussam Amrouch
University of Stuttgart (Germany)
|"Reliability Challenges in Emerging Negative Capacitance Transistors"|
|Dr. Thomas Dalgaty
CEA-Leti (Grenbole, France)
|"RRAM for stochastic neural network"|
|Prof. Mai-Khanh Nguyen
University of Tokyo (Japan)
SOITEC Institut National Polytechnique de Grenoble (France)
|"FD-SOI, the opportunity for edge computing applications"|
Tsinghua University (Peking, China)
|"System and technology co-optimization for RRAM-based computation-in-memory chip"|
IMEC (Löwen, Belgien)
|"CMOS compatible GaN-on-Si HEMT technology for RF applications: analysis of substrate losses and no-linearities"|
National University of Singapore (Singapore)
|"Oxide semiconductor-based transistors for 3D monolithic integration"|
|Prof. Suting Han
Shenzhen University (China)
|"Function memristor for in-sensor computing"|
|Prof. Hao Gao
Eindhoven University of Technology (Netherlands)
|"Silicon-based sub-THz PA for wireless communication”|
|Prof. Aimin Song
University of Manchester (UK)
|"Thin-film transistors that are immune to short-channel effect for low-power circuit applications"|
|Prof. Yung C. Liang
National University of Singapore (Singapore)
|"High-sensitivity AlGaN/GaN magnetoresistive sensor device by profiling the AlGaN layer"|
|Prof. Hongxia Liu
Xidian University (China)
|"Research on Transparent Resistive Random Memory Based on Lanthanum-based High-K Medium"|
|Prof. Jacopo Franco
IMEC (Löwen, Belgien)
|"Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies"|
|Prof. Suting Han
Shenzhen University (China)
|Prof. Zhigang Ji
Shanghai Jiaotong University (China)
|"Design and Implementation of the low power random number generator using nano-scaled transistors"|
|Prof Jiang Xu
Hong Kong University of Science and Technology (China)
|"Rejuvenate Post-Moore's Law Computing with Photonics-Electronics Hybrid Systems"|
|Prof Chun Zhao
Xi'an Jiaotong-Liverpool University (China)
|"Advanced synaptic transistor device towards AI application in hardware perspective"|
|Prof. Xiaodong Huang
Southeast University (China)
|"Effects of back interface on performance of dual-gate InGaZnO thin-film transistor with an unisolated top gate structure"|
|Prof. Cheng Ran
Zhejiang University (Hangzhou, China)
|"A ballistic transport study for advanced transistors in post-More era: parasitic resistance, self-heating, and cryogenic analysis"|
|Prof. Ni Kai
Rochester Institute of Technology (New York, US)
|"In-memory computing using ferroelectrics"|
CEA-Leti (Grenbole, France)
|"2.5D with active interposer (2.5D/3D)"|
Tutorials are about 1.5 hours long with additional discussion time. Tutorials will take place on Wednesday, September 15, 2021 and can be booked optionally in addition to the conference. Please click the registration tab for more info.
|#1 GaN power devices: from technology to reliability challenges||Dr. Matteo Meneghini (University of Padova, Italy)|
|#2 Large-Scale Silicon Photonic MEMS Switches||Prof. Ming Wu (Berkeley University, USA)|
|#3 Plasma-induced damage (Process and device design)||Andreas Martin (Infineon Technologies AG, Germany)|
|#4 Neuromorphic Computing for Edge AI||Dr. Thomas Kämpfe (Fraunhofer IPMS, Germany)|
Dr. Matteo Meneghini (University of Padova, Italy)
GaN power devices have excellent properties for application in the power conversion field. The wide bandgap, the high sheet channel density, the large breakdown field permit to substantially increase performance and reduce losses, compared to conventional silicon devices. Different device structures are available, from lateral normally-off transistors, to fully vertical device architectures. This tutorial reviews the main properties of gallium nitride, and the unique characteristics of GaN-based devices. Details on lateral and vertical device architectures will be given, to present a comprehensive overview on the topic.
In the second part of the presentation, the main reliability challenges for GaN devices will be discussed, with focus on dynamic on-resistance and breakdown phenomena. Finally, perspectives in the GaN field will be presented.
Prof. Ming Wu (Berkeley University, USA)
Silicon photonics has emerged as a promising solution to address the interconnect bottleneck in high performance computing systems and data centers. Silicon photonics provides unprecedented I/O bandwidth, enabling ultrahigh aggregated bandwidth (~ 10 Tbps), high bandwidth density (~ Tbps/mm), and high energy efficiency (~ pJ/bit). In addition, silicon photonics also enable optical switching with large port count and short switching time.
This talk will provide an overview of the state of the art of silicon photonic switches, with emphasis on new micro-electro-mechanical-system (MEMS)-actuated switching mechanism. Large scale (240x240) switches have been demonstrated, as well as wavelength-selective switches with 8x8 ports and 8 wavelengths.
Future scaling to even larger port count will be discussed.
Andreas Martin (Infineon Technologies AG, Neubiberg, Germany)
Plasma processing induced charging damage (PID) is a serious reliability risk for designs of integrated circuits of various processing nodes and several device types. Dependent on the type/style of design the sensitivity to PID can vary significantly. The most prominent degradation is reported for MOS transistors, but also integrated capacitors can suffer degradation or even dielectrics between metal lines in the metal stack. Any type of technology can be affected implemented on bulk-silicon or on SOI with dielectrics such as SiO2 as well as high-K materials. The reliability risk for a productive circuit is supposedly eliminated by so-called antenna design rules. The maximum metal area causing the charging event is limited in the design manual. However the antenna design rules are only sufficient when the PID reliability stress characterization throughout the process qualification has a high grade and is complete. The incorporation of all possible degradation modes for the PID failure mechanism is essential but not necessarily accomplished. The open question is: “Are all PID risks covered by the rules in the design manual?”
In this tutorial the PID-basics such as antenna ratio, electron shading effect etc. are described briefly and furthermore pitfalls and new findings are highlighted, which could cause significant product risks depending on the layout style. An important topic are the protective devices against PID, their effectiveness is discussed. Aspects associated with 3D-systems are illustrated with respect to PID. Also the limitations of design rule checkers and circuit routing tools are described. The tutorial will give the “beginner” an introduction to the PID-topic while the advanced scientists gets a further perspective into the more or less hidden problem areas.
Dr. Thomas Kämpfe (Fraunhofer IPMS, Germany)
Neuromorphic Computing Technology is a brain-inspired sensing and processing hardware for more efficient and adaptive computing. It promises energy-efficient implementation of human cognition, such as interpretation and autonomous adaptation. Although the communication pathways in the brain and other neural systems cannot be directly translated into electronic circuits, these mathematical models provide the basis for the implementation. Various hardware realizations are currently discussed such as: mixed-signal analog/digital CMOS circuits, asynchronous event-based communication and processing schemes as well as memristive, phase-change, ferroelectric or spintronic devices, and other nano-technologies. In this tutorial we will introduce these realizations and discuss merits and challenges to reach the goal for efficient neuromorphic computing hardware for edge intelligence systems.
Registration is now open!
*Please send proof of enrolment at a university to firstname.lastname@example.org or fax it to +49/30/61 28 86 88, we will then send you a registration code.
The invoice for the conference registration is tax exempt according to § 4 No. 22a of German Value Added Tax Act (UStG).