MEMS Technologies

In addition to the conceptual design, development and fabrication of MEMS and MOEMS devices, Fraunhofer IPMS possesses the know-how for the fabrication of individualized BSOI wafers, the electrical characterization of devices and develops suitable packaging solutions following fabrication.

MEMS Technology Analysis - Electrical Characterization

Characterization at wafer level

To characterize the complex devices and technologies, Fraunhofer IPMS is able to perform the following measurements (in-/ex-situ) both at wafer level and on the individual device:

  • Mixed-signal testing
  • Parametric test system
  • Electro-optical test system for micro-displays and sensors
  • Sensor-actuator test system
  • Non-electrical test
  • Optical inspection
  • CV analysis
  • Insulator integrity and reliability characterization


Pick and place of a SLM

Wafers can be thinned for the manufacturing of BSOI wafers by means of CMOS-compatible grinders. Furthermore, Fraunhofer IPMS recently enhances BSOI wafers with novel features, such as cavities, buried guideways or even multi-SOI structures.

Further bonding capabilities are:

  • Direct bonding (Si / SiO2 , Si / Si and plasma-assisted bonding).
  • Adhesive bonding (BCB bonding)
  • Thermocompression bonding
  • SOI-design and manufacturing

Packaging and Assembly

Packaging and Assembly at Fraunhofer IPMS Dresden

MEMS devices open up new possibilities in the miniaturization of systems. Fraunhofer IPMS offers corresponding development services to help our customers create innovative products. However, the system design using MEMS, electronics, optics and other photonic components and the processes for assembling the systems in the smallest volumes are mutually dependent. Fraunhofer IPMS therefore has the necessary expertise and equipment for microassembly and also offers small batch manufacturing as a service.


System development and small batch manufacturing

  • System development and system realization from one source
  • Realization of two- and multi-component superstructures
  • Realization of 2D and 3D superstructures

More about our Packaging and Assembly services.

Intelligent BSOI wafers

BSOI wafers according to customer requirements

The increasing demand for BSOI wafers, coupled with the requirements for our sophisticated components, have led Fraunhofer IPMS to build up competencies in the field of BSOI manufacturing in recent years. In doing so, our approach addresses individualized solutions for our customers in BSOI wafer fabrication. The devicelayers are equipped with various features, such as an adapted layer thickness and adapted doping. Thanks to our many years of technological experience, add-ons such as cavities or buried conductor paths can also be integrated into the device layer. This enables our customers to make optimum use of resources and short process times in the development of sophisticated products. The necessary technology modules are available to us and are completed by the following capabilities:

  • Grinding tool for thinning
  • 5-zone CMP for planarization
  • Bonder for bonding top and bottom wafers

Surface Micromechanics

Principle of surface micromechanics

Using sacrificial layer technology, Fraunhofer IPMS is able to manufacture actuators and sensors such as surface light modulators (SLM) and capacitive ultrasonic sensors (CMUT). The processes and technology modules available to Fraunhofer IPMS for these highly complex components are:

  • PE-CVD for TEOS, HDP and a:Si.
  • Five-zone CMP for high planarity
  • Anti-stiction for excellent reliability
  • PVD for joints and mirrors with stress tuning
  • ALD for barrier coatings
  • Gas phase etching using HF and XeF2 for sacrificial layer processing

Volume Micromechanics

Principle of volume micromechanics

Whether high-precision mirrors or the unique Nano-E-Drive principle developed by Fraunhofer IPMS: these actuators are based on deeply etched silicon structures with large aspect ratios (up to 40). In addition to the competencies in surface micromechanics, the following modules are available for further development:

  • Grinder for wafer thinning
  • PVD for highly reflective layers
  • Wafer bonding for quasi-static motion
  • Deep silicon etching for the realization of comb drives
  • TMAH etching for backside openings
  • Trench backfill for insulation
  • B-SOI wafers as starting materials

Monolithic MEMS-on-CMOS Integration

Integration of MEMS on CMOS

Monolithic integration of MEMS on CMOS is an integration technology for the fabrication of wafer-level integrated systems. Fraunhofer IPMS develops and manufactures monolithically integrated MEMS to minimize parasitic effects. With this technology, especially large devices with a high integration density can be realized reliably. Examples are SLMs, thermopile and CMUT arrays.

Active Silicon

© Fraunhofer IPMS
Ion-sensitive field-effect transistor of the Fraunhofer IPMS

Fraunhofer IPMS manufactures wafer-level devices that exploit the chemical and physical properties of functional layers, for example in the ion-sensitive field-effect transistor for measuring pH values. Our technology experts have extensive knowledge and experience regarding the interaction between materials and device physics.

  • Thermal oxidation for gate oxides (SiO2)
  • Annealing (RTP/RTA)
  • Deposition of active layers (e.g. Ta2O5)