Electrical Sensors

Organic field effect transistors (OFET)#

OFET waferstack
© Fraunhofer IPMS
OFET structure.

If an (organic) semiconductor layer is deposited on such a substrate, the Si bulk takes over the gate function and controls the current flow between the gold electrodes. A suitably doped Si-SiO2 interface in CMOS quality guarantees a reproducible gate contact. The gold electrodes with patented adhesive layer suppress the formation of injection barriers between the gold electrodes and the organic in the transistor channel, even for p-type semiconductors, so that reliable ohmic source / drain contacts are formed in the OFET.

Due to their reliability and reproducible preparation, these substrates are used worldwide by all major developers of organic semiconductor materials as part of standardised material monitoring.

In the standard OFET layout, a 200 mm wafer has almost 1800 individual transistors on 112 chips, each sized at 15 × 15 mm². Each chip carries four groups with four identical transistors, with a channel length of 2.5, 5, 10, 20 μm respectively). Identical layouts with graded channel widths as well as a flexible selection of the oxide thickness allow the adjustment to a broad voltage and conductivity range of the test materials. Customer-specific layouts with different electrode geometries are possible at any time. In advantage for our customers, beside the wafers we offer wafflepacks with 16 seperated chips.

Lateral Organic Field Effect Transistors (LOFET)#

LOFET waferstack
© Fraunhofer IPMS
LOFET structure.

Another step to simplify material characterisation is the analysis of basic logic circuits. For this purpose, up to 36 individual transistors are connected to form inverter and ring oscillators. Monitoring the active materials then only requires a frequency measurement of the ring oscillators, which can be automated with little effort. The much more time-consuming measurement and evaluation of the individual transistor characteristics can be omitted. Furthermore, one not only obtains reliable information on the logic capability, but at the same time determines the dynamic properties of the inverters.

The available layout of the logic circuits includes a first block with eleven individual transistors, which enables a complete parameter extraction for the circuit simulation. A second block contains four inverters, which are identically found in the oscillator stages. These separately accessible inverter stages allow a detailed analysis of the transient behaviour in case the amplification of the individual inverter stages is not sufficient for the ring oscillators to start oscillating. The third block contains ring oscillators with seven or fifteen stages. Each ring circuit has a three-stage output amplifier that decouples the oscillation in the ring from the output, as well as allowing direct frequency measurement without external amplification.

The LOFET substrates are also realised in bottom-gate architecture, so that after deposition of the semiconductor layer on the chip, functional circuits are available.