FPGA and SoC Design Services

FPGA and SoC Design Services

Fraunhofer IPMS provides you with comprehensive advice on all queries relating to FPGA development and develops IP cores and SoCs according to your requirements. The multidisciplinary IP design team at Fraunhofer IPMS with specialist knowledge of domain-specific computer architectures, RTL design and the implementation of electronic systems is available as a competent development partner for mixed-signal systems at every stage of development.

 

 

Compentencies and expertise

Hardware description languages

  • VHDL/Verilog

 

Design Tools

Design modelling:

  • MathWorks® Matlab® / MathWorks Simulink®
  • Xilinx System Generator for DSP

Design entry:

  • VHDL | Verilog
  • Altera QSYS® | Altera SOPC Builder
  • Lattice Semiconductor Mico32 SDT
  • Xilinx EDK | Xilinx Vivado® IP Integrator

Verification:

  • Mentor Graphics ModelSim® PE (VHDL | Verilog | Code Coverage)
  • Vivado HLS

Synthesis, place and route, static timing analysis:

  • Altera Quartus II | Lattice Diamond | Lattice iceCube2 | Microsemi Libero
  • Xilinx ISE | Xilinx Vivado | Xilinx Vitis+

 

Selection of FPGAs and SoCs

Altera®:

  • Stratix® I / Cyclone® V / Cyclone® V SoC / Cyclone® IV / Cyclone® III
  • MAX® V / MAX® II

Microsemi®:

  • ProASIC®3

Xilinx®:

  • Zynq®-7000 | Kintex®-7 | Artix®-7 | Virtex®-6 | Virtex-5 | Virtex-4
  • Spartan®-6 | Spartan®-7 | Spartan-3A DSP | Spartan-3E | Spartan-3
  • CoolRunner™ II | XC9500XL