FPGA and SoC Design Services

FPGA and SoC Design Services

Fraunhofer IPMS is happy to provide you with comprehensive advice on all questions relating to FPGA development and develops IP cores and SoCs according to your requirements. The multidisciplinary IP design team of Fraunhofer IPMS with expertise in domain-specific computer architectures via RTL design to the implementation of electronic systems is available to you as a competent development partner for mixed-signal systems at every stage of development.

Competences & Expertise

Hardware description languages

  • VHDL/Verilog

Design tools

Design modeling:

  • MathWorks® Matlab® / MathWorks Simulink®
  • Xilinx System Generator for DSP


  • VHDL | Verilog
  • Altera QSYS® | Altera SOPC Builder
  • Lattice Semiconductor Mico32 SDT
  • Xilinx EDK | Xilinx Vivado® IP Integrator


  • Mentor Graphics ModelSim® PE (VHDL | Verilog | Code Coverage)
  • Vivado HLS

Synthesis, place and route, static timing analysis:

  • Altera Quartus II | Lattice Diamond | Lattice iceCube2 | Microsemi Libero
  • Xilinx ISE | Xilinx Vivado | Xilinx Vitis+


Selection of FPGAs and SoCs used


  • Stratix® I / Cyclone® V / Cyclone® V SoC / Cyclone® IV / Cyclone® III
  • MAX® V / MAX® II


  • ProASIC®3


  • Zynq®-7000 | Kintex®-7 | Artix®-7 | Virtex®-6 | Virtex-5 | Virtex-4
  • Spartan®-6 | Spartan®-7 | Spartan-3A DSP | Spartan-3E | Spartan-3
  • CoolRunner™ II | XC9500XL